Leads design verification for Cerebras AI chip architecture, developing scalable SystemVerilog/UVM environments, tests, assertions, and coverage plans while debugging across simulation, emulation, and silicon bring-up. Requires 10+ years of verification experience and strong programming and hardware-debugging skills.
Leads post-silicon bring-up and optimization of Cerebras Wafer Scale Engines, developing validation infrastructure, diagnostics, testing automation, and performance improvements across hardware and software. Requires 7–10+ years of industry experience and strong ASIC, coding, debugging, and cross-functional collaboration skills.
Design and lead FPGA-based host and network IO systems spanning chassis-to-wafer communication, RoCE networking, switching fabrics, and proprietary serial IO. The role requires production FPGA experience, Verilog expertise, timing closure, and network protocol/debugging knowledge.
Develop and review electrical infrastructure designs for high-density AI data center clusters, translating system power requirements into safe, scalable facility architectures. Requires 7+ years experience with mission-critical facilities, power distribution equipment, and electrical studies.
Lead the technical development of data center infrastructure standards and deployment designs for high-density AI systems, owning the Basis of Design for power, cooling, mechanical and electrical infrastructure while partnering with internal engineering teams and external colocation providers.
Debug and root-cause complex electrical, thermal, and mechanical failures in Cerebras' massive AI compute systems both in-lab and in the field. Drive learnings back into next-generation hardware design while remotely diagnosing deployed systems using Linux tools.
Serve as owner's technical representative providing mechanical infrastructure oversight for high-density AI data center deployments. Review designs, manage colocation partners, support construction/commissioning, and ensure operational readiness of cooling systems (8+ years mission-critical/hyperscale data center experience required).
Design, implement, and optimize automated manufacturing assembly and test systems using PLCs, robotics, and industrial controls. Requires 3+ years in manufacturing automation, strong troubleshooting skills, and a bachelor's in engineering.
Senior Systems Engineering Technician responsible for building, testing, and troubleshooting complex mechanical, electrical, and water-cooled hardware systems in a prototype lab. Requires 5+ years hands-on multidisciplinary experience, independent work with incomplete documentation, and strong mechanical/electrical diagnostic skills.
Design and analyze 3D integrated ASIC/SoC products, performing physical verification, power/clock/cooling analysis, and collaborating with RTL teams on novel 3D packaging concepts. Requires 10+ years of physical design experience and expertise with ICV/Calibre, IR/EM, and scripting.
Design and develop next-generation Wafer Scale Engine chips with deep RTL expertise, focusing on high-performance, power-efficient micro-architecture and integration. Requires 8+ years RTL experience and a Master's degree.
Architect new AI chip features by translating specs into micro-architecture requirements, building performance/power models, and conducting PPA trade-offs. Requires 10+ years in performance modeling for GPUs/CPUs/accelerators and a Master's or PhD.
As a Mechanical Engineer, you will lead the design of mechanical systems for next-generation wafer-scale engines, ensuring compliance, manufacturability, and high-quality product delivery in a fast-paced AI environment. You will develop mechanical infrastructure for custom hardware systems and collaborate with cross-functional teams.
Performs post-silicon validation, testing, and debugging of wafer-scale AI chips and high-speed interfaces. Develops automation scripts in Python/Bash and collaborates on hardware bring-up and system diagnostics. Requires Master's in EE/CE and 3+ years experience.
Designs and analyzes 3D integrated ASIC/SoC products, optimizing power, performance, area, and handling verification, IR/EM, packaging, and cooling. Requires 10+ years experience in physical design flows, scripting, and 3D stacking technologies.
Leads RTL design and integration for next-generation wafer-scale AI chips, driving micro-architecture, synthesis, vendor management, and collaboration with verification/physical design teams. Requires 8-15 years experience in high-performance RTL, networking protocols, and Master's degree.
Performs physical design for AI silicon chips, including synthesis, place & route, timing closure, and verification for high-speed wafer-scale architectures. Requires 10+ years experience with EDA tools and scripting.
Leads PCB design from specification to production, handles schematic design, component selection, lab bring-up, and debugging. Requires 5-10 years experience in board design, electrical engineering degree, and skills in digital circuits, power delivery, and Python scripting.
Supports manufacturing system bring-up by configuring, testing, validating, and debugging complex computer systems before shipment. The role requires 3+ years of operations experience, hardware and ASIC bring-up expertise, and scripting skills in Python or Perl.
Owns the server platform architecture for Cerebras AI clusters, translating runtime workloads into CPU, memory, I/O, PCIe, networking, and firmware requirements. The role requires deep Linux and x86 expertise, performance modeling, benchmarking, vendor leadership, and 8–10+ years of relevant industry experience depending on degree.
Leads post-silicon bring-up, debugging, testing, and performance optimization for Cerebras Wafer Scale Engines. The role requires 7–10+ years of experience, substantial pre- and post-silicon ASIC expertise, strong programming and automation skills, and cross-functional collaboration across hardware and software teams.
Leads design verification for Cerebras AI chip architecture, developing scalable SystemVerilog/UVM environments, tests, assertions, and coverage plans while debugging across simulation, emulation, and silicon bring-up. Requires 10+ years of verification experience and strong programming and hardware-debugging skills.
Leads post-silicon bring-up and optimization of Cerebras Wafer Scale Engines, developing validation infrastructure, diagnostics, testing automation, and performance improvements across hardware and software. Requires 7–10+ years of industry experience and strong ASIC, coding, debugging, and cross-functional collaboration skills.
Design and lead FPGA-based host and network IO systems spanning chassis-to-wafer communication, RoCE networking, switching fabrics, and proprietary serial IO. The role requires production FPGA experience, Verilog expertise, timing closure, and network protocol/debugging knowledge.
Develop and review electrical infrastructure designs for high-density AI data center clusters, translating system power requirements into safe, scalable facility architectures. Requires 7+ years experience with mission-critical facilities, power distribution equipment, and electrical studies.
Lead the technical development of data center infrastructure standards and deployment designs for high-density AI systems, owning the Basis of Design for power, cooling, mechanical and electrical infrastructure while partnering with internal engineering teams and external colocation providers.
Debug and root-cause complex electrical, thermal, and mechanical failures in Cerebras' massive AI compute systems both in-lab and in the field. Drive learnings back into next-generation hardware design while remotely diagnosing deployed systems using Linux tools.
Serve as owner's technical representative providing mechanical infrastructure oversight for high-density AI data center deployments. Review designs, manage colocation partners, support construction/commissioning, and ensure operational readiness of cooling systems (8+ years mission-critical/hyperscale data center experience required).
Design, implement, and optimize automated manufacturing assembly and test systems using PLCs, robotics, and industrial controls. Requires 3+ years in manufacturing automation, strong troubleshooting skills, and a bachelor's in engineering.
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Senior Systems Engineering Technician responsible for building, testing, and troubleshooting complex mechanical, electrical, and water-cooled hardware systems in a prototype lab. Requires 5+ years hands-on multidisciplinary experience, independent work with incomplete documentation, and strong mechanical/electrical diagnostic skills.
Design and analyze 3D integrated ASIC/SoC products, performing physical verification, power/clock/cooling analysis, and collaborating with RTL teams on novel 3D packaging concepts. Requires 10+ years of physical design experience and expertise with ICV/Calibre, IR/EM, and scripting.
Design and develop next-generation Wafer Scale Engine chips with deep RTL expertise, focusing on high-performance, power-efficient micro-architecture and integration. Requires 8+ years RTL experience and a Master's degree.
Architect new AI chip features by translating specs into micro-architecture requirements, building performance/power models, and conducting PPA trade-offs. Requires 10+ years in performance modeling for GPUs/CPUs/accelerators and a Master's or PhD.
As a Mechanical Engineer, you will lead the design of mechanical systems for next-generation wafer-scale engines, ensuring compliance, manufacturability, and high-quality product delivery in a fast-paced AI environment. You will develop mechanical infrastructure for custom hardware systems and collaborate with cross-functional teams.
Performs post-silicon validation, testing, and debugging of wafer-scale AI chips and high-speed interfaces. Develops automation scripts in Python/Bash and collaborates on hardware bring-up and system diagnostics. Requires Master's in EE/CE and 3+ years experience.
Designs and analyzes 3D integrated ASIC/SoC products, optimizing power, performance, area, and handling verification, IR/EM, packaging, and cooling. Requires 10+ years experience in physical design flows, scripting, and 3D stacking technologies.
Leads RTL design and integration for next-generation wafer-scale AI chips, driving micro-architecture, synthesis, vendor management, and collaboration with verification/physical design teams. Requires 8-15 years experience in high-performance RTL, networking protocols, and Master's degree.
Performs physical design for AI silicon chips, including synthesis, place & route, timing closure, and verification for high-speed wafer-scale architectures. Requires 10+ years experience with EDA tools and scripting.
Leads PCB design from specification to production, handles schematic design, component selection, lab bring-up, and debugging. Requires 5-10 years experience in board design, electrical engineering degree, and skills in digital circuits, power delivery, and Python scripting.
Supports manufacturing system bring-up by configuring, testing, validating, and debugging complex computer systems before shipment. The role requires 3+ years of operations experience, hardware and ASIC bring-up expertise, and scripting skills in Python or Perl.
Owns the server platform architecture for Cerebras AI clusters, translating runtime workloads into CPU, memory, I/O, PCIe, networking, and firmware requirements. The role requires deep Linux and x86 expertise, performance modeling, benchmarking, vendor leadership, and 8–10+ years of relevant industry experience depending on degree.
Leads post-silicon bring-up, debugging, testing, and performance optimization for Cerebras Wafer Scale Engines. The role requires 7–10+ years of experience, substantial pre- and post-silicon ASIC expertise, strong programming and automation skills, and cross-functional collaboration across hardware and software teams.