Host and Network IO FPGA Engineer

Responsibilities

• Lead full chassis-to-wafer IO architecture and design.
• Improve current RTL, implement next-generation FPGA designs, and define future IO architectures.
• Produce production-ready bitstreams for deployment into large clusters running customer inference services.
• Work with the design verification team to prevent bug slips and simplify debugging.
• Optimize bandwidth and latency across FPGA datapaths and all IO interfaces.
• Interface with board teams to facilitate and execute board bring-up.
• Drive network performance debugging of large AI clusters.
• Integrate leading-edge networking technologies and protocols.
• Lead cross-functional technical projects spanning multiple teams and integrating software and hardware components.
• Foster clear and effective communication across teams and stakeholders.

Requirements

• 5+ years of industry experience generating production FPGA solutions, or a master's/PhD in Computer or Electrical Engineering plus 3 years of industry experience.
• Proficiency in Verilog development in a Git-based repository.
• Strong productivity with FPGA placement and routing, timing closure, simulation, debugging, and related FPGA workflows.
• Familiarity with network protocols including TCP and RoCE.
• Experience with network debugging tools such as Wireshark.
• Knowledge of network switch environments such as Arista and Juniper, or willingness to learn.
• Experience optimizing FPGA datapaths and IO interfaces for bandwidth and latency.

Compensation and Benefits

• Work on a breakthrough AI platform and high-performance AI supercomputers.
• Opportunities to publish and open-source cutting-edge AI research.
• Startup vitality with job stability and a non-corporate work culture.
• Continuous learning, growth, and support in an inclusive work environment.