Skip to content
Cerebras SystemsCerebras SystemsSunnyvale, CA

ASIC Architect

Architect new AI chip features by translating specs into micro-architecture requirements, building performance/power models, and conducting PPA trade-offs. Requires 10+ years in performance modeling for GPUs/CPUs/accelerators and a Master's or PhD.

Salary not listed
On-site10+ YOEHardware Engineering

About the role

Responsibilities

  • Translate high level architecture spec to micro-architecture feature requirements
  • Bring up new features in the performance/power model
  • Perform comprehensive PPA trade-offs for new architectural features
  • Extract insights for new features and micro-architecture power efficiency
  • Profile workloads, identify bottlenecks and project competition performance for benchmarking
  • Engage with SW teams for end-end application level modeling at cluster level
  • Identify kernel level HW acceleration level opportunities

Qualifications

  • Masters/PhD in Electrical/Computer Engineering
  • 10+ years of experience across performance analysis and modeling across GPUs, CPUs or accelerator products
  • Strong background in computer architecture and key high level architectural trade-offs
  • Comfortable standing up new performance models from scratch in Python or similar analytical environments
  • Exposure to micro-code (kernel) performance bottlenecks and optimization techniques
  • Good understanding of how high-level workloads map to underlying micro-architecture is desired
  • Understanding of basic ML workload profiling techniques and model network architecture is preferred

Skills

PythonComputer ArchitecturePerformance ModelingGpu ArchitectureCpu ArchitecturePpa AnalysisWorkload ProfilingMicro-ArchitectureMl Workload AnalysisPerformance Analysis
Crusoe

Staff Hardware Systems Engineer

CrusoeSan Francisco, CA +1

Staff Hardware Systems Engineer responsible for full lifecycle of high-performance GPU/CPU compute systems at Crusoe, with deep focus on debugging and validation of PCIe, InfiniBand, and NVMe/storage subsystems. Requires 8+ years experience, strong hardware expertise, and automation skills to ensure reliability and scalability of AI infrastructure.

208k – 253k/yr
On-site8+ YOEHardware Engineering
OpenAI

Data Center Research & Development Engineer, Mechanical

OpenAISan Francisco, CA

Lead R&D for next-generation data center power, cooling, and high-performance computing infrastructure at OpenAI. Oversee design validation, lab buildout, testing of high-voltage systems and liquid-cooled racks, and vendor collaboration for large-scale AI deployments. Requires 20+ years experience in critical data center systems.

260k – 385k/yr
On-site20+ YOEHardware Engineering
OpenAI

Data Center Design Engineer, Electrical

OpenAISan Francisco, CA

Lead electrical and MEP design, operation, and maintenance for large-scale AI data center campuses at OpenAI. Requires 10+ years in critical infrastructure, deep expertise in power/cooling systems, vendor management, and a PE license.

360k – 530k/yr
Hybrid10+ YOEHardware Engineering
Shield AI

Staff Engineer, Landing Gear Systems

Shield AIDallas, TX

Staff Engineer responsible for the full mechanical design lifecycle of electro-mechanical and hydro-mechanical landing gear systems for autonomous UAVs, including concept development, CAD, analysis, prototyping, testing, and cross-functional collaboration with avionics and structures teams.

130k – 200k/yr
On-site7+ YOEHardware Engineering
Shield AI

Staff Engineer, Mechanical & Actuated Systems

Shield AIDallas, TX

Staff Mechanical & Actuated Systems Engineer responsible for designing complex electro-mechanical mechanisms, actuators, and systems for autonomous UAVs. Owns full design cycle from concept through analysis, prototyping, testing, and production release on the X-BAT platform. Requires 7+ years mechanical design experience, strong CAD/FEA skills, and aerospace background.

130k – 200k/yr
On-site7+ YOEHardware Engineering