Lead RTL Design Engineer
Leads RTL design and integration for next-generation wafer-scale AI chips, driving micro-architecture, synthesis, vendor management, and collaboration with verification/physical design teams. Requires 8-15 years experience in high-performance RTL, networking protocols, and Master's degree.
About the job
Responsibilities
- Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
- Managing external ASIC vendor through product development cycle.
- Work closely with PD team members for design closure to meet PPA goals.
- Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
- Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
- Debug silicon-level functional, timing, and power issues during bring up.
Requirements
- Master's degree in Computer Science, Electrical Engineering, or equivalent.
- 8-15 years of experience in delivering complex, high performance high quality RTL designs.
- Experience with Front End Chip integration and third-party IP integration.
- Demonstrated experience in networking, high-performance computing, machine learning or related fields.
- Proven track record of multiple silicon success.
- Experience collaborating and managing external vendors.
- Experience with designing/integrating high speed IO.
- Networking stack experience including TCP/IP, RDMA and Ethernet.
- Knowledge of PCIe, CPU interfaces and Serdes technology.
- Working knowledge of scripting tools: Python, TCL.
Assets
- Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis.
Compensation
- Base salary range: $175,000 to $275,000 annually. Actual compensation may include bonus and equity.
Skills
Rtl, Verilog, Systemverilog, Synthesis, Asic, Fpga, Python, Tcl, Pcie, Serdes, TCP/IP, Rdma, Ethernet, High-Speed Io
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