Staff Design Verification Engineer

Responsibilities

• Work with architects, designers, post-silicon, and software engineers to ensure high-quality designs work on first silicon.
• Develop and implement verification strategies, detailed tests, and coverage plans based on microarchitecture.
• Create verification methodologies and reusable environments, including stimulus, checkers, assertions, and coverage.
• Implement tests, manage regressions, gather coverage, and debug test failures.
• Collaborate with architecture, RTL design, physical design, firmware, and validation teams.
• Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
• Enhance verification infrastructure and flows to improve efficiency and quality.
• Contribute to verification methodology and best practices across the organization.

Requirements

• 10+ years of design verification experience.
• Strong debugging and problem-solving skills.
• Deep knowledge of SystemVerilog testbenches, DPI, and UVM.
• Excellent programming skills and software engineering practices, including object-oriented design.
• Experience developing scalable and portable testbenches and components.
• Experience with verification methodologies and tools, including simulators, waveform viewers, build and run automation, coverage collection, and gate-level simulation.
• Proficiency in Python or Perl.
• Strong interpersonal and collaboration skills.
• Self-motivated and eager to solve problems.
• Bachelor's or master's degree in Computer Science or Electrical Engineering.

Nice-to-haves

• Knowledge of pipelined processor architecture.

Compensation

• Base salary range: $250,000–$300,000 annually.
• Actual compensation may include bonus and equity and will be determined by experience, skills, and qualifications.