Physical Design Engineer

Responsibilities

• Design and analysis of 3D integrated products
• Work on traditional ASIC/SoC physical design, packaging, power, clock, and cooling analysis
• Collaborate with architecture and RTL teams on R&D for novel 3D integration concepts
• Perform block-level and full-chip physical verification
• Optimize for power, performance, and area
• Execute complete physical design flow
• Resolve block and full-chip DRC and LVS issues using ICV or Calibre
• Conduct IR/EM analysis and resolution
• Create flow enhancements using scripting (Tcl, Python)
• Work with RTL teams to optimize physical design
• Apply knowledge of 2.5D or 3D packaging solutions, 3D physical design, 3D die stacking, 3D chip design, die-to-die or wafer-to-wafer

Requirements

• 10+ years of physical design/verification experience
• Strong knowledge of block level and full-chip physical verification methodology
• Expert at optimizing for power/performance and area
• Experience with complete physical design flow; Synopsys tool suite knowledge is a plus
• Expert with ICV or Calibre tools for DRC and LVS issues
• Expert with IR/EM analysis and resolution
• Strong scripting ability in Tcl and Python for flow enhancements
• Demonstrated ability to work with RTL teams
• Knowledge of 2.5D or 3D packaging solutions
• Experience with 3D physical design, 3D die stacking, 3D chip design, die-to-die or wafer-to-wafer

Nice-to-Haves

• Experience with full chip floor planning and integration
• Knowledge of clock distribution
• Knowledge of cooling analysis

Compensation

• Salary range: $230,000 – $280,000 annually
• Actual compensation based on experience, skills, qualifications, and location