Design and develop next-generation Wafer Scale Engine chips with deep RTL expertise, focusing on high-performance, power-efficient micro-architecture and integration. Requires 8+ years RTL experience and a Master's degree.
250k – 300k/yr
On-site8+ YOEHardware Engineering
About the role
Responsibilities
Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
Work closely with PD team members for design closure to meet PPA goals.
Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
Debug silicon-level functional, timing, and power issues during bring up.
Requirements
Master’s degree in Computer Science, Electrical Engineering, or equivalent.
8+ years of experience in delivering complex, high performance high quality RTL designs.
Experience with Front End Chip integration and third-party IP integration.
Demonstrated experience in networking, high-performance computing, machine learning or related fields.
Proven track record of multiple silicon success.
Experience collaborating with external vendors.
Networking stack experience including TCP/IP, RDMA and Ethernet.
Knowledge of PCIe, CPU interfaces and Serdes technology.
Working knowledge of scripting tools: Python, TCL.
Nice-to-Haves
Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis.
Experience managing external ASIC vendor through product development cycle.
Compensation
Base salary range: $250,000 to $300,000 annually.
Actual compensation may include bonus and equity.
Skills
RtlMicro-ArchitectureSynthesisFront End Chip IntegrationIp IntegrationNetworkingHigh-Performance ComputingMachine LearningTCP/IPRdmaEthernetPcieSerdesPythonTcl
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