Senior RTL Engineer, Interconnect Design

Responsibilities

• Own the microarchitecture, RTL design, and delivery of major SoC interconnect components, including network-on-chip fabrics, switches, routers, bridges, protocol adapters, arbiters, and traffic-management logic as well as off-chip protocol bridges and interfaces.
• Drive third party engagements to develop novel networking and interface protocols and silicon IP while ensuring high quality and design integrity.
• Perform substantial direct microarchitecture and RTL coding work.
• Collaborate with architecture and design team members on the overall solution and execution plan for cutting-edge large-scale custom silicon.
• Work with performance and architecture teams to analyze traffic patterns, identify bottlenecks, and optimize interconnect behavior under realistic system workloads.
• Collaborate with design verification teams to develop verification strategies, coverage plans, assertions, stress scenarios, and debug approaches for highly concurrent fabric behavior.
• Partner with physical design teams to ensure interconnect structures are implementable at target frequency, power, and area, including floorplan-aware design, pipeline strategy, timing closure, and congestion management.
• Provide technical leadership through design reviews, architecture reviews, documentation, mentoring, and development of reusable RTL and integration methodologies.

Requirements

• Extensive industry experience designing and delivering complex SoC interconnect, NoC, coherent fabric, memory subsystem, cache-coherent, or chip-level integration solutions.
• Strong track record of owning major RTL blocks or SoC subsystems from microarchitecture through tape-out and silicon bring-up.
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• Strong understanding of interconnect concepts such as topology, routing, arbitration, virtual channels, flow control, buffering, ordering, quality of service, coherency, deadlock avoidance, congestion management, and performance monitoring.
• Experience with common on-chip or chip-to-chip protocols and interfaces, such as AXI, APB, CXL, PCIe, Ethernet.
• Experience building custom networking protocols or protocol extensions.
• Experience designing and implementing subsystems in the context of large scale systems built with RDMA/RoCE or other HPC-style system-level interconnects.
• Familiarity and deep experience with the full spectrum of industry-standard RTL-adjacent development and signoff flows, including lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, and design-for-test considerations.
• Experience working closely with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
• Strong judgment in making practical design tradeoffs across performance, power, area, schedule, verification risk, and physical implementation constraints.
• Excellent communication skills and the ability to provide technical direction, mentor engineers, and drive alignment across multiple teams.

Nice-to-Haves

• Experience designing interconnect for AI accelerators, GPUs, CPUs, high-performance computing systems, networking silicon, or large-scale datacenter silicon.
• Experience with memory consistency, virtualization, isolation, RAS, telemetry, or security requirements within complex SoCs.
• Experience with NoC performance modeling, traffic simulation, emulation, FPGA prototyping, or post-silicon performance analysis.
• Experience leading architecture or RTL delivery for first-generation silicon programs or rapidly evolving hardware platforms.