Senior Product Manager, Hardware (NPU IP)

Responsibilities

• Own Quadric's TOPS/W and area-per-TOPS targets for QD; identify PPA risks at iso-process node and drive tradeoff conversations before silicon freezes.
• Translate customer requirements, competitive pressure, and architectural constraints into a track-by-track feature list (Compute, Efficiency, Scalability, Safety, Integration) with explicit gating.
• Build the case for contested architecture decisions, run tradeoffs with architects, and bring recommendations to the PSC.
• Serve as named hardware product owner for anchor accounts; present new features, ingest architecture feedback, and convert it into roadmap input.
• Identify customer workarounds (API wrappers, glue logic, custom RTL hooks) and convert repeated patterns into QD features.
• Track competitors (Synopsys NPX6, Arm Ethos-U85, Ceva NeuPro-M, VeriSilicon Vivante, NVIDIA Jetson) at the architectural level; deliver two formal PPA teardowns per year.
• Decide which SoC integration knobs (AXI4/ACE-Lite, CoreSight, power-domain partitioning, performance counters) are exposed and productized.
• Sequence FMEDA work, lockstep configurations, and safety-island architecture decisions from ASIL-B to ASIL-D.

Requirements

• 5–8 years of PM experience on hardware or silicon products with senior IC background.
• Fluency in NPU/compute architecture (dataflow, memory hierarchy, MAC arrays, bandwidth vs. compute), datatypes and quantization (INT4/INT8/FP8/BF16/OCP MX), SoC integration (AMBA AXI4/ACE-Lite, CoreSight, power domains), functional safety (ISO 26262, FMEDA, lockstep, ASIL-B/D), and competitive landscape.
• Track record running architecture reviews with Tier 1 automotive and OEM SoC teams.
• Experience with IP licensing cycles (18–24 months integration before silicon).
• Daily use of agentic AI tools (Claude Code, Cursor, or equivalent).
• Customer-first mindset prioritizing workable solutions over elegant engineering.
• Direct experience with at least two of: NPU/AI accelerator architecture, SoC integration, DSP/vector compute, automotive silicon, semiconductor IP licensing.
• EE/CE/CS engineering degree or equivalent depth.
• Experience with in-person technical customer reviews.
• Bay Area resident or willing to relocate to Burlingame.

Nice-to-Haves

• RTL or silicon-implementation background (shipped a block, tape-out experience, or owned microarchitecture spec).
• Prior IP vendor experience (Synopsys, Arm, Ceva, Cadence, Imagination, VeriSilicon, Rambus, or similar).
• Direct exposure to AI/ML compute stack architecture (dataflow, quantization, sparsity, mixed-precision).
• Japanese-market customer experience.

Benefits

• Competitive salary and meaningful equity.
• Medical, dental, and vision starting day one.
• 401(k) retirement plan.
• Unlimited flexible PTO.
• Company-provided lunches and stocked kitchen.
• Monthly parking or Caltrain pass.
• Downtown Burlingame office near Caltrain.