Design Verification Engineer
Develops AI-assisted verification workflows and reusable frameworks using SystemVerilog, UVM, and Python for silicon IP blocks. Owns strategy, coverage, debug, and tapeout readiness while collaborating with ML teams; requires 4-6 years verification experience.
About the job
What You’ll Do
- Own verification strategy across multiple IP blocks and subsystems, from testbench architecture to signoff.
- Design and develop AI assisted workflows that accelerate verification, coverage closure, and debug.
- Build reusable verification frameworks using SystemVerilog, UVM, Python and custom automation tooling.
- Collaborate with ML and software teams to integrate AI models into existing DV environments.
- Contribute to product direction by exploring how automation can reshape verification methodologies.
- Work with customers in a forward deployed capacity when needed, translating real design challenges into product features.
- Drive tapeout readiness with full accountability for quality metrics, regression health, and coverage targets.
- Mentor junior engineers and help define best practices for next generation verification teams.
Qualifications
- 4 to 6 years of hands-on verification experience.
- Strong SystemVerilog and UVM skills with proven debug depth.
- Familiarity with Python or similar scripting languages.
- Curious mindset toward AI or automation in verification, even if not an expert yet.
- Ability to work across domains and communicate clearly with software or ML teams.
- Comfortable interacting with clients, architects, and leadership when needed.
- Thrives in a high responsibility environment and enjoys creating solutions that did not exist before.
Bonus Skills
- Experience with formal verification, co-simulation or stimulus generation frameworks.
- Background in ML, LLMs, data pipelines, or tool development.
- Previous involvement in customer facing or forward deployed engineering roles.
- Demonstrated ability to build tools that others actually use.
Skills
Systemverilog, Uvm, Python, Formal Verification, AI, Machine Learning, Co-Simulation, Stimulus Generation, Testbench Architecture, Coverage Closure
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