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Voltai

AI foundation models for semiconductor design

aiMenlo Park, CA51-200Series AOnsiteFounded 2016
About

Voltai develops foundational AI models and agentic systems to accelerate innovation in semiconductors and electronics design. They optimize complex engineering processes for automotive, consumer electronics, IoT, and semiconductor manufacturing. This enables breakthroughs beyond human cognitive limits in design productivity.

Tech stack
CUDASystemVerilogUVMMPIPythonC++PyTorchJiraTypeScriptReactTensorFlowCagentic workflowsvLLMProcess AutomationTelemetryNext.jsClay
Open roles 25

Senior Forward Deployed Engineer (FDE)

Own customer deployments and develop AI platform features for semiconductor and electronics companies. Requires 5+ years backend/full-stack/infra experience, cloud and Docker fluency, and willingness to travel within California.

Palo Alto, CASolutions ArchitectureOn-site5+ YOEGoAWS

Strategic Projects Lead

Leads end-to-end delivery of complex cross-functional technical programs in AI/ML, data operations, engineering, and product evaluation. Aligns stakeholders, manages scope/resources, builds scalable workflows/data pipelines, and coordinates distributed teams. Requires master's degree and 4+ years in engineering-related roles.

183k – 192kMenlo Park, CATechnical Program ManagementOn-site4+ YOEJiraAI/ML

Special Projects

Executes high-ownership special projects end-to-end in a fast startup, working directly with leadership on highest-leverage initiatives. Requires experience running complex projects, outreach tools proficiency, strong design/presentation/writing skills, and scrappiness in novel challenges.

Palo Alto, CAOtherOn-siteClayHunter

BizOps

Manages day-to-day operations by monitoring KPIs, optimizing processes, automating systems, ensuring compliance, and collaborating across departments to support business scaling and efficiency.

Palo Alto, CA +1Business OperationsOn-siteKpi AnalysisData Analysis

Computational Scientist

Develops and scales MPI+CUDA PDE solvers and neural operators for electromagnetic simulations on GPU clusters for IC design. Requires PhD in computational physics/math, expertise in numerical methods, C++/CUDA, HPC, and neural operators for physics problems.

Palo Alto, CA +1ML EngineeringOn-siteC++Mpi

Field Application Engineer (Europe)

Provides technical support to integrate hardware and design systems with customer workflows, debugs complex software/hardware issues, and relays requirements to product teams. Requires 5+ years in hardware design/EDA and customer support skills.

United StatesSales EngineeringRemote5+ YOEEda ToolsDebugging

Hardware Application Engineer

Integrates hardware and design systems with customer workflows, provides technical support, debugs software/hardware issues, and relays requirements to product teams. Requires 5+ years in hardware design, EDA tools, and customer support.

Palo Alto, CA +1Hardware EngineeringOn-site5+ YOEEda ToolsDebugging

Lab Automation Engineer

Designs and maintains automation infrastructure for hardware validation labs, building systems to test and qualify silicon and board designs using software, robotics, and data pipelines. Requires 5+ years in Python/LabVIEW, instrumentation control, and hardware bring-up.

Palo Alto, CAEmbedded EngineeringOn-site5+ YOEPxiScpi

Server Hardware Engineer

Designs, brings up, and validates compute/storage hardware platforms for AI-driven workloads. Requires 5+ years in server/board design, signal/power integrity, thermal/mechanical systems, and post-silicon validation.

Palo Alto, CA +1Hardware EngineeringOn-site5+ YOEBoard DesignServer Design

Network Development Engineer

Designs and deploys high-performance network architectures for compute infrastructure and distributed AI simulation environments. Optimizes for latency, throughput, fault tolerance; requires 5+ years in high-speed networking protocols like Ethernet, InfiniBand, RDMA.

Palo Alto, CADevOps / SREOn-site5+ YOERdmaRouting

System Architect

Defines architecture for advanced AI-integrated compute and hardware systems, balancing power, performance, and scalability. Requires 5+ years in SoC/system architecture, hardware/software co-design, and interface design.

Palo Alto, CASolutions ArchitectureOn-site5+ YOEAi Co-DesignSoc Architecture

Power Electronics Engineer

Designs and optimizes power conversion/distribution systems for AI hardware, including topologies, simulations, and validation of thermal/EMI performance under extreme conditions. Requires 5+ years in switch-mode supplies, GaN/FET, SPICE/PLECS, and power system expertise.

Palo Alto, CA +1Hardware EngineeringOn-site5+ YOESpicePlecs

System Engineer

Defines, models, and integrates complex electromechanical and computational systems from simulation to silicon, owning system-level architecture. Requires 5+ years in systems engineering for semiconductors, robotics, or compute systems with cross-functional collaboration skills.

Palo Alto, CA +1Embedded EngineeringOn-site5+ YOERoboticsHardware

Formal Verification Engineer

Develops formal proofs for hardware design correctness using model checking and property verification. Collaborates with RTL and ML teams on hybrid engines for AI-generated hardware, requiring 5+ years in formal tools like JasperGold.

Palo Alto, CABackend EngineeringOn-site5+ YOESvaRtl

Design Verification Engineer

Develops AI-assisted verification workflows and reusable frameworks using SystemVerilog, UVM, and Python for silicon IP blocks. Owns strategy, coverage, debug, and tapeout readiness while collaborating with ML teams; requires 4-6 years verification experience.

Palo Alto, CA +1QA EngineeringOn-site4+ YOEAIUvm

Research Engineer - CUDA Kernel Engineering

Develops and optimizes CUDA kernels for AI models accelerating semiconductor design, verification, and chip optimization across large-scale GPU clusters. Integrates with frameworks like PyTorch and latest NVIDIA hardware for training, inference, and RL workloads.

Palo Alto, CABackend EngineeringOn-siteCUDANccl

Research Engineer - Mid-Training

Trains frontier LLMs on semiconductor design/verification data (RTL, netlists, PDKs) for automated chip development. Develops synthetic data generation, model distillation, evals, and scales training across thousands of GPUs.

Palo Alto, CAML EngineeringOn-siteRtlLLMs

Research Engineer - Post-Training

Post-trains frontier AI models using reinforcement learning to autonomously handle semiconductor design tasks like chip architecture optimization, RTL code generation, simulations, and verification. Collaborates with hardware experts to build RL environments, reward functions, and evaluation frameworks.

Palo Alto, CAML EngineeringOn-siteRtlLLMs

Firmware Engineer

Designs and implements firmware bridging AI hardware with physical devices, handling bring-up, control, diagnostics for real-time self-optimizing systems. Requires 5+ years in C/C++, RTOS/bare-metal, board bring-up, and debug tools.

Palo Alto, CAEmbedded EngineeringOn-site5+ YOECC++

Full Stack Engineer

Builds scalable full stack solutions including backend, frontend, and complex agentic workflows for AI-driven hardware and semiconductors. Requires 3+ years experience with React, TypeScript, Python, Next.js, C++ from top-tier CS/EECS programs.

Palo Alto, CAFullstack EngineeringOn-site3+ YOEC++React

Enterprise Program Manager

Coordinates cross-functional teams to deliver enterprise products, manage customer requests, demos, and PoCs while driving engineering execution. Requires 3-5+ years in customer-facing program/product management/sales and comfort with EE/PCB topics.

Palo Alto, CA +1Technical Program ManagementOn-site3+ YOESalesPcb Design

Enterprise Sales Executive

Prospects and closes large enterprise deals in semiconductor and electronics sectors, building client relationships and collaborating with engineering teams. Requires 5+ years sales experience leading enterprise deals and bachelor's in EE/Physics or related.

United StatesAccount ExecutiveRemote5+ YOEPocsPhysics

Engineering Manager

Leads a team of 3-8 engineers in sprint-based delivery for AI/hardware projects, prioritizing work, translating requirements into tasks, removing blockers, and driving process improvements. Requires 2-6 years engineering management experience with agile tools like Jira/Linear and technical depth.

Palo Alto, CA +1Engineering ManagementOn-siteJiraLinear

Software Engineer

Builds complex agentic workflows and AI systems for hardware, electronics, and semiconductors using Python, C++, TypeScript, and React. Requires 3+ years experience from top-tier CS/EECS programs.

Palo Alto, CAFullstack EngineeringOn-site3+ YOEC++React

Machine Learning Engineer

Develops and deploys AI/ML models including fine-tuning LLMs and multi-modal systems from concept to production. Requires strong AI/ML skills from top CS/EECS/Math/Physics programs and proven production experience.

Palo Alto, CAML EngineeringOn-siteLLMsPyTorch