Senior Design Verification Engineer

Leads architecture and implementation of SoC-level verification environments for GPNPU-based ASICs, using UVM, SystemVerilog/Verilog, VCS, co-simulation, assembly, and Python. Requires at least five years of complex SoC/ASIC design verification experience.

About the job

Responsibilities

Testbench Architecture & Test Plan Development

Architect and build scratch-built testbenches for SoC-level verification of GPNPU-based SoCs.
Collaborate with architects, hardware designers, and software teams to document comprehensive verification test plans.
Implement scalable testbenches using commercial Verification IP (VIP) and internal software utilities.

Test Execution & Verification Coverage

Develop directed and random drivers, assembly programs, and C++ programs to stress-test SoC subsystems and integration.
Verify complex SoC subsystems and third-party IP, including NoC, PCIe/UCIe, and DDR.
Use VCS and Verilog/C co-simulation environments, assembly programming, and Python scripting to execute test suites.
Track, analyze, and communicate verification progress using functional and code coverage metrics.

Requirements

5+ years of dedicated design verification experience on complex SoC/ASIC designs.
Deep expertise in UVM methodology and SoC-level verification practices.
Proficiency in SystemVerilog or Verilog, assembly programming, and Python.
Hands-on experience verifying SoC subsystems and third-party IP such as NoC, PCIe/UCIe, and DDR.
Strong computer architecture background.
Experience with VCS and Verilog/C co-simulation.

Compensation & Benefits

Competitive salary.
Medical, dental, and vision insurance.
Equity with the business.
Paid parental leave.
PF retirement plan.
Flexible PTO.
Winter holiday shutdown.
Catered lunch each day in the office.
Downtown Pune office location.
Collaborative culture with significant ownership and impact.

Skills

Uvm, Systemverilog, Verilog, Python, C++, Assembly Programming, Vcs, Verilog/C Co-Simulation, Soc Verification, Asic Design, Pcie, Ddr, Noc, Computer Architecture, Functional Coverage