Senior Hardware Engineer - Micro-Architect
Designs and implements microarchitecture and RTL for innovative neural processing unit using SystemVerilog/SystemC. Optimizes PPA, contributes to timing closure, requires 5+ years CPU/GPU/ASIC experience and strong computer architecture background.
About the job
Responsibilities
- Contribute to the definition of the processor architecture by understanding its applications
- Own microarchitecture definition & RTL implementation of the processor in SystemC or SystemVerilog
- Own Power, Performance & Area (PPA) optimization
- Contribute to timing closure through full product cycle (front end, back-end, tapeout)
Requirements
- BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design
- Proficiency in SystemC, SystemVerilog, or Verilog
- Strong background in computer architecture
- Knowledge of design techniques for low power digital design
- Knowledge of VCS & Verilog/C Co-Sim
- Experience in data-parallel hardware design for high-performance computing
Nice to Haves
- Experience in FPGA design
- Experience in logic synthesis and performance modeling
- Familiarity with automotive safety (ASIL) standards
Expected Outcomes in 12 months
- Independently own a major design block and improve PPA
- Develop an in-depth understanding of the architecture and SW interfaces and be able to debug issues across the full SW/HW stack
- Package design for customer releases and incorporate customer feedback
Skills
Systemverilog, Systemc, Verilog, Rtl, Computer Architecture, Low Power Design, Vcs, Verilog/C Co-Sim, Data-Parallel Hardware, Fpga, Logic Synthesis, Performance Modeling
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