Silicon Engineer

Responsibilities

• Participate in end-to-end program activities, including strategy, specification, execution, and setting the technical bar.
• Write specifications and interface definitions that guide design work and remain coherent as the architecture converges.
• Own directional decisions involving technology and IP selection, build-versus-buy-versus-license choices, and design authority versus partner reliance.
• Develop and share AI-assisted approaches for code-like work in silicon engineering and evaluate where Claude can accelerate workflows.
• Contribute domain-specific perspectives to architecture and microarchitecture discussions, including tradeoffs imposed on the rest of the chip.
• Partner with inference, performance, kernels, infrastructure, and hardware systems teams on hardware-software co-design, bring-up, and integration.
• Support first-silicon bring-up and debugging across domains.

Minimum Qualifications

• Deep, hands-on expertise in at least one silicon domain: front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, technology and foundry, design infrastructure, or packaging and signal/power integrity.
• Direct personal contribution to silicon that taped out and shipped, with detailed ownership of the work.
• Working fluency in adjacent domains sufficient to reason about chip-level tradeoffs.
• Experience working with external ASIC houses, IP vendors, foundries, or test partners, including reviewing work and maintaining a technical bar.
• Track record of owning directional technical decisions and their consequences.
• Practical experience using AI coding tools and clear judgment about their strengths and limitations.
• Clear written and verbal communication, with experience driving alignment across teams and organizations.
• Comfort operating autonomously with limited scaffolding on a dynamic program.

Preferred Qualifications

• Experience with machine learning accelerators, high-performance computing, or other large, high-bandwidth designs.
• Experience on a founding or early-stage silicon team, including establishing flows, methodology, or tooling.
• Experience with both partner-executed and fully in-house programs.
• Familiarity with chip-package-system interfaces and cross-layer tradeoffs.
• Experience with hardware-software co-design and direct collaboration with compiler, kernel, or runtime teams.
• Experience building or extending AI-assisted design, verification, or physical design flows.
• Depth in memory subsystems, on-die interconnect, numerics, or low-power design.

Representative Projects

• Write specifications for compute datapaths and defend numeric-format strategies.
• Establish front-end flows and release management, then hand releases to an ASIC partner.
• Run in-house place-and-route loops on critical blocks and feed PPA findings into architecture.
• Select and qualify PHY IP and validate it on first silicon.
• Build formal verification methodologies and determine where formal methods outperform simulation.
• Define test strategies and automated-test-equipment handoff interfaces.
• Prototype Claude-assisted workflows for RTL review, coverage triage, or specification consistency checking.
• Debug first-silicon failures spanning multiple domains.

Compensation and Benefits

• Annual salary range: $320,000–$485,000 USD.
• Minimum education: bachelor's degree or equivalent combination of education, training, and experience.
• Relevant field of study demonstrated through coursework, training, or professional experience.
• Hybrid policy: staff are currently expected to work from an office at least 25% of the time; some roles may require more.
• Visa sponsorship may be available.