ASIC Package SI/PI Engineer
Owns signal-integrity and power-integrity architecture, modeling, optimization, and validation for advanced AI ASIC packages. The role requires at least five years of high-speed interconnect and package electrical-design experience, plus expertise with electromagnetic and SI/PI simulation tools.
About the job
Responsibilities
- Own signal integrity and power integrity architecture and analysis for advanced AI ASIC packages from feasibility through production.
- Develop and optimize high-speed electrical channels for 200G/400G SerDes, PCIe, HBM, DDR, and chiplet/die-to-die interfaces.
- Model packages, interposers, and substrates using 2D/3D electromagnetic solvers.
- Define and optimize package stack-ups, transmission-line structures, via transitions, breakout structures, return paths, ground shielding, bump maps, and ball maps.
- Develop channel loss, crosstalk, impedance, skew, return-loss, and link-budget requirements and translate them into package layout guidelines.
- Perform package-level PDN analysis, including impedance, loop inductance, DCIR, electromigration, dynamic voltage droop, current distribution, decoupling optimization, and power/ground architecture.
- Drive die/package co-design, including bump/BGA assignment, stack-up optimization, power/ground allocation, high-speed I/O placement, and package routing architecture.
- Develop automated simulation methodologies and design-optimization flows for model extraction, simulation setup, post-processing, design-space exploration, and SI/PI sign-off.
- Collaborate across ASIC, package, PCB, system, mechanical, thermal, power, silicon validation, and manufacturing teams.
Requirements
- 5+ years of experience in signal integrity, power integrity, high-speed interconnect design, PDN design, and package electrical design.
- Strong understanding of transmission-line behavior, impedance, loss, crosstalk, return paths, power-distribution networks, inductance, decoupling, voltage droop, and current distribution.
- Hands-on experience with electromagnetic and SI/PI simulation tools such as Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI, Sigrity PowerDC, or equivalent.
- Experience with package layout environments such as Cadence APD/SIP, including reviewing and modifying package structures for SI/PI optimization.
- Experience developing automated design-optimization flows for model extraction, simulation setup, post-processing, design-space exploration, or layout optimization.
- Strong communication and cross-functional collaboration skills.
Nice-to-haves
- Experience with advanced 2.5D/3D packaging, silicon or organic interposers, bridge technologies, HBM integration, IVR integration, or large-body AI/HPC packages.
- Experience developing early-stage SI/PI feasibility methodologies for chip and package architecture decisions.
- Experience with HBM and DDR/LPDDR memory architectures and high-speed memory interfaces.
- Experience with VNA, spectrum analyzers, TDR/TDT, high-bandwidth oscilloscopes, and probe-based measurements.
- Knowledge of package and PCB material properties, including dielectric constant, loss tangent, copper roughness, and manufacturing variation.
Compensation
- Annual salary range: $266,000-$445,000.
Skills
Signal Integrity, Power Integrity, Serdes, Pcie, Hbm, Ddr, Electromagnetic Solvers, Hspice, Hfss-Pi, Siwave, Cadence Clarity, Cadence Apd/Sip, Sigrity Powersi, Sigrity Powerdc
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