Advanced Technology: Compiler Engineer

What You Will Do

• Design and implement compiler passes across the Tungsten toolchain: mid-end optimization, backend code generation, instruction scheduling, register allocation, assembler, and linker.
• Co-design language constructs that improve expressiveness and performance for dataflow execution on wafer-scale hardware.
• Develop and iterate on code generation strategies for complex scientific and AI workloads, analyzing performance bottlenecks and closing the gap between peak and achieved throughput.
• Extend the compiler to support future hardware architectures as they move from design to silicon.
• Work directly with ASIC architects and application researchers to inform hardware-software co-design decisions.

What We Are Looking For

• PhD in Computer Science or Computer Engineering preferred; exceptional candidates without a graduate degree who demonstrate equivalent depth through published research, significant open-source contributions, or a strong industry track record are encouraged to apply.
• Substantial experience in compiler development: IR design, optimization passes, code generation, or backend implementation for novel or non-standard architectures.
• Strong grasp of computer architecture: instruction sets, memory models, dataflow execution, and how hardware constraints shape compilation strategy.
• Systems-level programming ability in C; comfort reasoning about performance at the instruction and memory-access level.
• Ability to think about compilation as a design problem, not just an implementation task: you should have opinions about how language semantics, compiler IR, and hardware capabilities interact.
• Excellent communication and interpersonal skills: able to work effectively in a small, fast-moving team where compiler, architecture, and application concerns are deeply intertwined.

Valuable Assets

• Experience with compilers for spatial, dataflow, or CGRA architectures where the compilation model diverges significantly from conventional CPU/GPU targets.
• Exposure to ML compiler frameworks (MLIR, XLA, TVM) and understanding of how AI workloads map to hardware.
• Experience with multi-dimensional data representations, tiling strategies, and vectorized operations.
• Track record of published research or patents in compilers, programming languages, or architecture.
• Experience building runtime systems, debuggers, or architecture simulators, particularly for non-standard hardware.
• Understanding of parallel/distributed systems and cluster computing.