Senior Electrical Engineer responsible for architecture and system-level design of high-speed digital compute and power electronics for phased array ground stations. Owns electrical architecture decisions, system trades, schematic review, and cross-functional collaboration with RF, FPGA, and firmware teams. Requires 5-7+ years experience in high-density/high-speed design and ability to obtain Top Secret clearance.
122k – 250k/yr
On-site7+ YOEHardware Engineering
About the role
Responsibilities
Own the electrical architecture and system-level design for high-speed digital communication systems, defining how RF and mixed-signal designs, complex multi-layer PCBs, and subsystems fit together.
Define system-level architecture for multi-gigabit networking and complex digital power trees, and drive system trades that shape architecture decisions across the product.
Set technical direction and review schematic capture, layout, and bring-up across a variety of digital systems including FPGAs, microcontrollers, and their associated peripherals.
Collaborate across hardware and software teams with RF engineers, antenna engineers, FPGA engineers, and firmware engineers to optimize system performance and overall design.
Guide prototype testing and performance assessment in the lab and in the field, with an eye towards system-level root cause and risk.
Partner with production teams to ensure the overall system architecture supports testable and manufacturable products that we can integrate in-house.
Basic Qualifications
5-7+ years of professional experience in electrical design, including experience operating at the system or architecture level.
Proficient in high-density/high-speed design (including FPGAs, high speed data converters, SerDes, 10/100 GigE, networking, JESD204C).
Proficient in schematic capture and good PCB layout design.
Experience with troubleshooting EMI/EMC, either conducted or radiated.
Knowledge of PCB materials and developing board stack-up definition.
Experience with full product lifecycle (concept through production), including owning architecture-level decisions across that lifecycle.
Preferred Qualifications
5+ years of experience designing high-speed mixed-signal electronics and complex multilayer PCBs for FPGA- or processor-based systems.
Strong expertise in high-speed interfaces and networking technologies such as multi-gigabit SerDes, DDR, JESD204B/C, and 10/100G Ethernet.
Deep understanding of signal integrity, power integrity, EMI/EMC mitigation, PCB stack-up definition, and high-performance board layout practices.
Proven experience leading hardware development from architecture and prototype bring-up through validation, manufacturing, and production ramp.
Hands-on experience debugging complex hardware systems using advanced lab instrumentation and driving root-cause analysis across board and system levels.
Ability to lead cross-functional technical efforts, mentor junior engineers, and make sound engineering tradeoffs in fast-paced development environments.
Additional Requirements
This position requires successfully obtaining and maintaining a Top Secret Security Clearance as a condition of employment.
Must be willing to work extended hours and weekends as needed.
Compensation
Electrical Engineer/Level 3: $122,400 - $153,000 per year
Electrical Engineer/Level 4: $144,000 - $180,000 per year
Electrical Engineer/Level 5: $180,000 - $225,000 per year
Electrical Engineer/Level 6: $204,000 - $255,000 per year
Base salary is just one part of your total rewards package at Northwood. In addition to base salary, Northwood Space offers long-term incentives such as company stock options and discretionary performance bonuses. Benefits include equity, comprehensive medical, vision, and dental coverage, flexible spending accounts, flexible time off, 10 or more paid holidays per year, retirement savings plans, and opportunities for professional development.
Skills
high-speed digital designfpgaserdesjesd204cpcb layoutsignal integritypower integrityemi/emcpcb stack-upschematic capturemulti-gigabit networking10/100g ethernetddr
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