Technical Program Manager, Silicon

Responsibilities

• Own the integrated silicon program plan, including architecture closure, RTL freeze, design verification milestones, IP delivery, physical-design closure, DFT, tapeout, and post-silicon bring-up.
• Drive execution across ASIC design partners, IP vendors, foundries, and packaging/test providers.
• Run technology and IP selection, evaluate vendors and options, and drive build, buy, and license decisions with engineering leadership.
• Build lightweight execution mechanisms, including milestone definitions, risk and dependency tracking, design reviews, release management, and executive reporting.
• Manage interfaces between silicon and hardware systems, including package, board, and bring-up activities, as well as inference, kernel, and compiler teams for hardware-software co-design.
• Own post-silicon activities, including bring-up planning, ATE/test handoff, sample distribution, validation, and production readiness.
• Develop AI-assisted approaches to program management, including schedule and dependency modeling, specification and milestone consistency checking, partner-deliverable tracking, and status synthesis.

Requirements

• 8+ years in silicon or SoC program management, chip leadership, or an equivalent role owning a chip schedule end to end.
• Direct ownership of at least one program that taped out and reached production.
• Technical fluency across the silicon lifecycle, including front-end design, design verification, physical design, DFT, foundry operations, and packaging.
• Experience managing external silicon partners, including ASIC houses, IP vendors, foundries, or OSAT providers; SOW scoping, delivery tracking, and escalation.
• Experience building program mechanisms from scratch for ambiguous, fast-moving efforts.
• Strong written communication for plans, reviews, and executive updates.
• Comfort operating autonomously with limited process.
• Bachelor's or master's degree in electrical engineering, computer engineering, computer science, or a related field, or equivalent experience.

Preferred Qualifications

• Experience with ML accelerators, high-performance computing, networking, or other large, high-bandwidth SoCs at advanced process nodes.
• Experience with first-generation or early silicon programs, including establishing flows, methodology, or vendor relationships.
• Experience with both partner-executed and fully in-house programs.
• Hands-on engineering experience in design, design verification, physical design, DFT, or SI/PI.
• Familiarity with chip-package-system interfaces and co-design with hardware systems teams.
• Experience with hardware-software co-design involving compiler, kernel, or runtime teams.
• Practical experience using AI tools in professional workflows.

Compensation

• Annual salary: $365,000–$435,000 USD
• Hybrid policy: Staff are expected to work from an office at least 25% of the time; some roles may require more office time.
• Visa sponsorship may be available depending on the role and candidate.