Develops tools, flows, and methodologies for physical implementation of AI accelerator silicon blocks. Owns floorplanning to signoff, optimizes PPA, and collaborates with RTL designers. Requires BS/MS/PhD with 2-4+ years in physical design.
266k – 445k/yr
On-site2+ YOEHardware Engineering
About the role
In this role, you will:
Develop, build and own tools, flows and methodologies for physical implementation
Own physical implementation of floorplan blocks from floorplanning to final signoff
Collaborate with RTL designers to drive optimal block implementation solutions
Analyze and optimize design for timing, power, and area trade-offs, working in collaboration with EDA vendors and ASIC partners
Qualifications:
BS w/ 4+ or MS with 2+ years or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
Demonstrated success in taping out complex silicon designs
Hands-on experience with block physical implementation and PPA convergence
Strong coding experience with python, bazel, TCL
Strong experience building physical design tools, flows and methodologies
Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification and timing closure
Deep familiarity with industry-standard tools and flows for physical synthesis, PNR, LEC and power estimation
Bonus:
Experience with AI or HPC-focused chips
Experience with optimizing PPA for high performance compute cores
Hands-on experience with top-level design methodologies
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