Senior Quantum Engineer, Gate Calibration

Responsibilities

• Lead experimental programs to characterize, calibrate, and optimize two-qubit gates on tunable-coupler devices, from single-pair physics investigations to full-processor deployment.
• Identify gate-error bottlenecks, including coherent control error, decoherence, leakage, crosstalk, and TLS interactions, and isolate their physical origins through targeted experiments, benchmarking, and simulation.
• Develop and harden calibration methods using optimal pulse shaping, dynamical decoupling, and other error-suppression strategies, emphasizing robustness and automation at scale.
• Develop and improve metrology for full-processor Hamiltonian and characteristic extraction, correlate it with gate performance, and turn findings into actionable feedback for device design, fabrication, and control-hardware teams.
• Prepare Rigetti devices for internal applications development teams and external deployment.
• Stay current with the literature and convert state-of-the-art techniques into working capability on production hardware.
• Contribute to superconducting quantum computing through high-quality publications.

Requirements

• PhD in Physics, Applied Physics, Electrical Engineering, or a related field.
• Significant hands-on experience calibrating and characterizing two-qubit gates on superconducting quantum devices; direct tunable-coupler experience is strongly preferred.
• Deep understanding of gate design, pulse engineering, and decoherence mechanisms, with demonstrated fidelity improvements from error diagnostics.
• Ability to independently execute complex experimental efforts from concept through validated results.
• Strong Python skills in a scientific context and experience building tools used by others.
• Experimental determination and judgment in balancing investigation depth with iteration speed.
• Excellent communication skills and a collaborative, team-first mindset.

Nice-to-haves

• Experience with quantum simulation frameworks such as QuTiP for gate and noise modeling.
• Experience deploying calibration or benchmarking procedures across large multi-qubit processors in an industrial or startup setting.
• Familiarity with randomized benchmarking variants, gate set tomography, cycle benchmarking, or other scalable error diagnostics.
• Publications or demonstrated results in high-fidelity entangling gates, error suppression, or quantum control.
• Experience mentoring junior scientists or leading small technical teams.