Skip to content
Applied IntuitionApplied IntuitionMountain View, CA

Software Engineer - Performance Optimization

Optimizes application-layer software for embedded systems in autonomous driving stacks, analyzing runtime performance, profiling compute resources on constrained platforms, and ensuring efficient execution while collaborating with ML engineers. Requires 5+ years experience, strong C++ skills, and bachelor's/master's in CS/EE.

199k – 265k
On-site5+ YOEEmbedded Engineering

About the role

Responsibilities

  • Analyze runtime performance of the application layer and identify potential resource contentions
  • Optimize compute usage to fit within embedded platform constraints without sacrificing algorithm accuracy or latency
  • Profile and tune performance on embedded targets under real-world operating conditions
  • Collaborate closely with ML runtime optimization engineers to ensure smooth model inference execution within the stack
  • Proactively design for contention avoidance and thread safety through code reviews and software architecture reviews; propose single threaded lock-free approaches where appropriate
  • Deploy and validate production code on QNX, Linux-based embedded, or similar RTOS platforms
  • Contribute to improving system-wide runtime, latency, and performance monitoring tools

Requirements

  • Bachelors or Masters in Electrical Engineering or Computer Science or a related field
  • 5+ years of experience in software development
  • Strong C++ development skills with a focus on runtime performance
  • Experience profiling CPU, GPU, and memory usage performance on constrained compute
  • Proven ability to debug complex runtime issues and resolve onboard resource contention

Nice to have

  • Exposure to ML models and runtime frameworks (PyTorch, ONNX, TensorRT)
  • Experience with memory-constrained deployments and concurrent scheduling
  • Prior experience with autonomous driving software stacks
  • Scripting experience for performance profiling and automation

Compensation

Base salary range: $199,295-$264,500 USD annually (full-time position). Total compensation may include equity, comprehensive health/dental/vision insurance, 401k with employer match, learning/wellness stipends, and paid time off.

Skills

C++QnxLinuxPyTorchOnnxTensorRTGPUCpu ProfilingMemory ProfilingRtosAutonomous DrivingLock-Free Programming
Fluidstack

Controls Systems Engineer, Deployment Engineering

FluidstackAustin, TX +3

Deploy and commission BMS, SCADA, and EPMS control systems for AI data centers, performing FAT, integration testing, sequence verification, and live handover while troubleshooting issues to ensure reliable operations. Requires bachelor's in engineering, hands-on industrial commissioning experience, and PLC/SCADA configuration skills; data center background preferred.

200k – 250k
Hybrid5+ YOEEmbedded Engineering
Fluidstack

Controls Engineer, PLC Programming

FluidstackAustin, TX +3

Develop and test reusable PLC control programs and sequences of operations for mechanical systems in large-scale AI data centers. Requires hands-on experience programming and wiring PLCs across multiple platforms, validating on real hardware in a lab.

200k – 250k
On-siteEmbedded Engineering
Zoox

Software Engineer - Core Sensors

ZooxFoster City, CA

Develops and maintains high-performance driver software for lidar, radar, and camera sensors critical to autonomous vehicle perception. Requires 5+ years experience, strong C++ proficiency, and device driver development expertise.

191k – 271k
Hybrid5+ YOEEmbedded Engineering
Rigetti Computing

IC Layout Automation Software Engineer

Rigetti ComputingFremont, CA

Develop and maintain software systems for IC layout generation supporting superconducting quantum circuit design and fabrication. Requires strong Python skills, GDSII experience, and familiarity with EDA tools and lithography processes.

190k – 220k
On-siteEmbedded Engineering
Cerebras Systems

Design Verification Engineer

Cerebras SystemsSunnyvale, CA

Develop verification strategies, reusable testbenches, and coverage plans for large-scale AI chip designs. Requires 3+ years of Design Verification experience with SystemVerilog, UVM, and strong debugging skills.

190k – 230k
On-site3+ YOEEmbedded Engineering