FluidstackAustin, TXDevelop and test reusable PLC control programs and sequences of operations for mechanical systems in large-scale AI data centers. Requires hands-on experience programming and wiring PLCs across multiple platforms, validating on real hardware in a lab.
Develop and test template PLC programs for standard mechanical equipment across data centers, including chiller skids, fan wall units, CRAHs, so one validated program deploys fleetwide.
Write portable code across mixed PLC hardware (Siemens, Codesys, virtualized PLCs).
Develop and tune sequences of operations (SOOs) with controls and mechanical teams, then implement those directly in PLC code.
Install and wire PLCs and sensors in a lab environment to validate programs before live deployment.
Debug programs against real IO and failure conditions on the bench.
Deploy and commission BMS, SCADA, and EPMS control systems for AI data centers, performing FAT, integration testing, sequence verification, and live handover while troubleshooting issues to ensure reliable operations. Requires bachelor's in engineering, hands-on industrial commissioning experience, and PLC/SCADA configuration skills; data center background preferred.
Optimizes application-layer software for embedded systems in autonomous driving stacks, analyzing runtime performance, profiling compute resources on constrained platforms, and ensuring efficient execution while collaborating with ML engineers. Requires 5+ years experience, strong C++ skills, and bachelor's/master's in CS/EE.
Develops and maintains high-performance driver software for lidar, radar, and camera sensors critical to autonomous vehicle perception. Requires 5+ years experience, strong C++ proficiency, and device driver development expertise.
Develop and maintain software systems for IC layout generation supporting superconducting quantum circuit design and fabrication. Requires strong Python skills, GDSII experience, and familiarity with EDA tools and lithography processes.
Develop verification strategies, reusable testbenches, and coverage plans for large-scale AI chip designs. Requires 3+ years of Design Verification experience with SystemVerilog, UVM, and strong debugging skills.