Responsibilities
- Work on design and analysis of 3D integrated products.
- Combine traditional ASIC/SoC physical design skills with packaging, power, clock, and cooling analysis.
- Collaborate with architecture and RTL teams on R&D for novel 3D integration concepts.
Required Qualifications
- 10+ years of physical design/verification experience.
- Strong knowledge of block level and full-chip physical verification methodology.
- Expert at optimizing for power/performance/area.
- Experience with complete physical design flow (Synopsys tool suite a plus).
- Expert with ICV or Calibre tools for resolving block and full-chip DRC/LVS issues.
- Expert with IR/EM analysis and resolution.
- Strong scripting in Tcl and Python for flow enhancements.
- Ability to work with RTL teams to optimize for physical design.
- Knowledge of 2.5D or 3D packaging solutions.
- Experience with 3D physical design, 3D die stacking, 3D chip design, die-on-die, or wafer-on-wafer.
Preferred Qualifications
- Experience with full chip floor planning and integration.
- Knowledge of clock distribution.
- Knowledge of cooling analysis.
Compensation
Salary range: $150,000 – $270,000 annually (based on experience, skills, qualifications, and location).