Leads end-to-end Design Validation Test (DVT) for complex electrical boards and systems, including power delivery, high-speed I/O validation, debug, and root-cause analysis. Requires 8+ years experience in hardware validation, strong EE skills, and lab equipment proficiency.
175k – 275k
On-site8+ YOEDevOps / SRE
About the role
What You’ll Own
1) Board / Subassembly DVT (EE-heavy)
Own DVT for complex PCBAs and subassemblies from first power‑on through design sign‑off.
Power validation: power‑up/down sequencing, regulator/hotswap behavior, rail margining, DC IR drop, and AC noise/ripple characterization.
Clock distribution validation and high‑speed I/O interface validation (e.g., Ethernet/PCIe-class links, board‑to‑board connectors and cabling).
Low‑speed system management interface validation (e.g., I2C/SPI/USB) and debug of intermittent or systemic failures.
Stress/environmental testing (extended runtime, temperature cycling) and characterization under margined conditions.
Own system integration validation planning and execution across representative configurations and operating envelopes.
Drive readiness and execution across lab and chamber environments, including dependency management (test scripts, instrumentation, SW readiness, sample availability).
Validate and debug system-level issues spanning electrical, mechanical, thermal, and optics interactions.
Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes.
Key Responsibilities
DVT Strategy, Plans, and Coverage
Define a risk‑based DVT strategy spanning board/subassembly engineering validation through system integration validation.
Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale.
Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness).
Hands-on Validation, Debug, and Closure
Build and own benchtop and rack-level validation setups that are repeatable and automation‑friendly.
Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re‑test and data review.
Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements.
Validate high‑speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers.
DVT Infrastructure, Automation, and Data
Partner with diagnostics/software to improve DVT throughput via scripting, logging, and standardized test stages.
Define required data capture and reporting standards to accelerate debug and support release gating.
Drive continual improvements to test coverage, efficiency, and repeatability across builds.
Cross-functional Technical Leadership
Align EE/ME/FW/Diagnostics/Reliability/Manufacturing on priorities, schedules, and closure criteria.
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