Latest QA Engineering jobs at Quadric
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Senior Design Verification Engineer
No salary listedOn-site5+ YOEQA Engineering
Leads architecture and implementation of SoC-level verification environments for GPNPU-based ASICs, using UVM, SystemVerilog/Verilog, VCS, co-simulation, assembly, and Python. Requires at least five years of complex SoC/ASIC design verification experience.