Design Verification Intern responsible for documenting test plans, writing/debugging tests, and generating coverage for CPU/GPU designs using SystemVerilog or similar. Must be pursuing a degree in CS or EE and available to work onsite in Burlingame, CA.
Designs and implements microarchitecture and RTL for innovative neural processing unit using SystemVerilog/SystemC. Optimizes PPA, contributes to timing closure, requires 5+ years CPU/GPU/ASIC experience and strong computer architecture background.
Design Verification Intern responsible for documenting test plans, writing/debugging tests, and generating coverage for CPU/GPU designs using SystemVerilog or similar. Must be pursuing a degree in CS or EE and available to work onsite in Burlingame, CA.
Designs and implements microarchitecture and RTL for innovative neural processing unit using SystemVerilog/SystemC. Optimizes PPA, contributes to timing closure, requires 5+ years CPU/GPU/ASIC experience and strong computer architecture background.