Research Engineer, Chip Design RL
Research Engineer advancing RL for silicon chip design at Anthropic. Design RL environments for RTL generation, verification, and physical optimization; requires deep ASIC/FPGA expertise from spec to tapeout.
About the job
Responsibilities
- Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
- Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
- Conduct experiments and shape our roadmap.
- Deliver your work into research and production training runs.
- Collaborate with other researchers and engineers across and outside Anthropic.
Requirements
- Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
- Fluent with industry EDA tools and processes.
- Taped out chips and experience going from spec to silicon.
- Know how to balance research exploration with engineering implementation.
- Passionate about AI's potential and committed to developing safe and beneficial systems.
- Bachelor’s degree or an equivalent combination of education, training, and/or experience in a relevant field.
Nice-to-Haves
- Experience with reinforcement learning, evaluations or environments.
- Built tooling or automation around chip design flows.
- Worked on ML accelerators or high-performance compute hardware.
- Familiarity with high-level synthesis or architecture simulators.
Skills
Reinforcement Learning, Rtl, Asic Design, Fpga Design, Uvm, Formal Verification, Eda Tools, Physical Design, Ppa Optimization, Dft, Ecos, Python
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