Research Engineer advancing RL for silicon chip design at Anthropic. Design RL environments for RTL generation, verification, and physical optimization; requires deep ASIC/FPGA expertise from spec to tapeout.
500k – 850k
Hybrid7+ YOEML Engineering
About the role
Responsibilities
Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
Conduct experiments and shape our roadmap.
Deliver your work into research and production training runs.
Collaborate with other researchers and engineers across and outside Anthropic.
Research Engineer advancing Claude's code generation capabilities through reinforcement learning. Design RL environments, build verifiers, run training experiments on frontier models, and improve training pipelines for real software engineering tasks.
500k – 850k
Hybrid7+ YOEML Engineering
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