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Research Engineer, Infrastructure, Kernels

350k – 475kSan Francisco, CADevOps / SREOnsite
Summary

Designs and optimizes high-performance ML kernels (CUDA, CuTe, Triton) for large-scale LLM training, focusing on GPU efficiency, low-precision formats, and distributed compute. Collaborates with researchers to bridge algorithms and hardware.

About the role

What You’ll Do

  • Design and implement custom ML kernels (e.g., CUDA, CuTe, Triton) for core LLM operations such as attention, matrix multiplication, gating, and normalization, optimized for modern GPU and accelerator architectures.
  • Design and think through compute primitives to reduce memory bandwidth bottlenecks and improve kernel compute efficiency.
  • Collaborate with research teams to align kernel-level optimizations with model architecture and algorithmic goals.
  • Develop and maintain a library of reusable kernels and performance benchmarks that serve as the foundation for internal model training.
  • Contribute to infrastructure stability and scalability, ensuring reproducibility, consistency across precision formats, and high utilization of compute resources.
  • Document and share insights through internal talks, technical papers, or open-source contributions to strengthen the broader ML systems community.

Skills and Qualifications

Minimum qualifications:

  • Bachelor’s degree or equivalent experience in computer science, electrical engineering, statistics, machine learning, physics, robotics, or similar.
  • Strong engineering skills, ability to contribute performant, maintainable code and debug in complex codebases.
  • Understanding of deep learning frameworks (e.g., PyTorch, JAX) and their underlying system architectures.
  • Thrive in a highly collaborative environment involving many, different cross-functional partners and subject matter experts.
  • A bias for action with a mindset to take initiative to work across different stacks and different teams where you spot the opportunity to make sure something ships.
  • Proficiency in CUDA, CuTe, Triton, or other GPU programming frameworks.
  • Demonstrated ability to analyze, profile, and optimize compute-intensive workloads.

Preferred qualifications:

  • Experience training or supporting large-scale language models with tens of billions of parameters or more.
  • Track record of improving research productivity through infrastructure design or process improvements.
  • Experience developing or tuning kernels for deep learning frameworks such as PyTorch, JAX, or custom accelerators.
  • Familiarity with tensor parallelism, pipeline parallelism, or distributed data processing frameworks.
  • Experience implementing low-precision formats (FP8, INT8, block floating point) or contributing to related compiler stacks (e.g., XLA, TVM).
  • Contributions to open-source GPU, ML systems, or compiler optimization projects.
  • Prior research or engineering experience in numerical optimization, communication-efficient training, or scalable AI infrastructure.

Logistics

Compensation: Depending on background, skills and experience, the expected annual salary range for this position is $350,000 - $475,000 USD.

Benefits: Generous health, dental, and vision benefits, unlimited PTO, paid parental leave, and relocation support as needed.

Skills
CUDACuTeTritonPyTorchJAXGPU programminglow-precision arithmetictensor parallelismpipeline parallelismXLATVM
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