# Senior Yield Enhancement Engineer
**Company:** [Cerebras Systems](https://hotfix.jobs/companies/cerebras-systems)
**Location:** Sunnyvale, CA
**Salary:** $175K-$250K
**Experience:** 7+ years
**Skills:** Ate, Failure Analysis, Yield Enhancement, Fib, Dft, Python, C/C++, Perl, Oscilloscopes, Wafer Probe Stations, Optical Inspection, Cmos Layouts, Sram, Obirch, Irem/Lada
**Posted:** 2026-04-15
> Senior Yield Enhancement Engineer analyzes ATE data logs and wafer defects, performs failure analysis using optical/FIB techniques, and drives yield improvements through collaboration with design, fab, and test teams. Requires 7+ years in semiconductor testing/FA and proficiency in Python/C++.
## Job Description
## Key Responsibilities

- Analyze ATE data logs, Shmoo plots, parametric characterization data, and spatial wafer defect patterns.
- Develop failure analysis tools using optical, photo emission, and laser-based defect localization techniques specific to Cerebras hardware.
- Develop and execute FIB (Focused Ion Beam) edit plans for Silicon root cause validation.
- Communicating with OSATs and Fab to drive production testing in HVM environment.
- Understand DFT strategies including hierarchical scan chains, distributed BIST, SRAM test methodologies, and perform diagnosis on ATE data.
- Collaborate closely with DFT engineers, silicon architects, designers, performance teams, and software engineers to enhance overall testability and yield.
- Refine test programs across di/dt behavior, voltage-frequency characterization space, current limits, and thermal constraints based on ATE logs and disposition learnings.
- Understand and write Python scripts and UNIX environment.

## Required Skills & Qualifications

- Bachelor's or Master's degree in Electrical Engineering / Computer Engineering, or related field.
- 7+ years of hands-on experience in semiconductor test engineering/ FA/ Yield Enhancement.
- Hands-on experience with lab debug tools including Oscilloscopes (high-speed probing and signal integrity), wafer probe stations, probe cards, Keyence/Optical inspection systems, and advanced imaging techniques.
- Failure analysis (FA) expertise including use of optical probing tools, physical inspection workflows, and correlation of electrical failures to physical defects.
- Strong capability to read and understand Digital CMOS layouts, power grids, routing structures and SRAM arrays.
- ATE test program debugging, and yield improvement experience.
- Working knowledge of git repositories, GitHub, git actions/Jenkins, merge and release flows to streamline test and release.
- Proficiency in programming languages: Python, C/C++, Perl for large-scale data analysis.

## Preferred Skills

- Develop fault isolation techniques using **OBIRCH/IREM/LADA** optical techniques.
- Experience with advanced test data analysis tools and machine learning techniques for yield optimization.
- Familiarity with advanced packaging technologies for wafer-scale systems (**TSV**, advanced interconnects).
- Familiarity with in-line testing and diagnostics using CPU memory and execution with self-checking.
- Knowledge of chip defect profiles and mitigation strategies across manufacturing steps.

## Compensation

Base salary range: **$175,000 to $250,000** annually. Actual compensation may include bonus and equity.
**Apply:** https://hotfix.jobs/jobs/senior-yield-enhancement-engineer-at-cerebras-systems-48180ee6-8b9c-4034-82cf-240f27a849f9
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