# Physical Design Engineer

**Company:** [Cerebras Systems](https://hotfix.jobs/companies/cerebras-systems)
**Location:** Sunnyvale, CA
**Role:** Hardware Engineering
**Salary:** $230k – $280k/yr
**Experience:** 10+ years
**Skills:** Physical Design, Asic, Soc, Physical Verification, Synopsys, Icv, Calibre, Drc, Lvs, Ir/Em Analysis, Tcl, Python, Rtl, 3D Integration, 2.5D Packaging
**Posted:** 2026-06-10

> Design and analyze 3D integrated ASIC/SoC products, performing physical verification, power/clock/cooling analysis, and collaborating with RTL teams on novel 3D packaging concepts. Requires 10+ years of physical design experience and expertise with ICV/Calibre, IR/EM, and scripting.

## Job Description

## Responsibilities
- Design and analysis of 3D integrated products
- Work on traditional ASIC/SoC physical design, packaging, power, clock, and cooling analysis
- Collaborate with architecture and RTL teams on R&D for novel 3D integration concepts
- Perform block-level and full-chip physical verification
- Optimize for power, performance, and area
- Execute complete physical design flow
- Resolve block and full-chip DRC and LVS issues using ICV or Calibre
- Conduct IR/EM analysis and resolution
- Create flow enhancements using scripting (Tcl, Python)
- Work with RTL teams to optimize physical design
- Apply knowledge of 2.5D or 3D packaging solutions, 3D physical design, 3D die stacking, 3D chip design, die-to-die or wafer-to-wafer

## Requirements
- 10+ years of physical design/verification experience
- Strong knowledge of block level and full-chip physical verification methodology
- Expert at optimizing for power/performance and area
- Experience with complete physical design flow; Synopsys tool suite knowledge is a plus
- Expert with ICV or Calibre tools for DRC and LVS issues
- Expert with IR/EM analysis and resolution
- Strong scripting ability in Tcl and Python for flow enhancements
- Demonstrated ability to work with RTL teams
- Knowledge of 2.5D or 3D packaging solutions
- Experience with 3D physical design, 3D die stacking, 3D chip design, die-to-die or wafer-to-wafer

## Nice-to-Haves
- Experience with full chip floor planning and integration
- Knowledge of clock distribution
- Knowledge of cooling analysis

## Compensation
- Salary range: $230,000 – $280,000 annually
- Actual compensation based on experience, skills, qualifications, and location

## Similar roles

- [Signal Integrity Engineer](https://hotfix.jobs/jobs/f7db798d-895a-4c55-b731-f5149e1d465a) - OpenAI - San Francisco, CA - $225k – $445k/yr
- [Senior/Staff Electrical Engineer, Compute](https://hotfix.jobs/jobs/a9d75e7a-6916-4d18-9b6d-0ba71070cd24) - Zoox - Foster City, CA - $217k – $300k/yr
- [Electrical Engineer, Staff](https://hotfix.jobs/jobs/5a173a9c-29bb-4ee3-b599-210c4262f93c) - 9 Mothers - Austin, TX - $250k – $400k/yr
- [Sr. Technical Staff](https://hotfix.jobs/jobs/6dff032f-f822-4a4c-a63f-4baa28e0a6ef) - Cerebras Systems - Sunnyvale, CA - $250k – $275k/yr
- [Staff Hardware Systems Engineer](https://hotfix.jobs/jobs/7e81320a-d04f-4250-a314-be3507991eff) - Crusoe - San Francisco, CA - $208k – $253k/yr

**Apply:** https://hotfix.jobs/jobs/f0c3730e-f7fc-4dc6-9cba-382f3efaa657
**Canonical:** https://hotfix.jobs/jobs/f0c3730e-f7fc-4dc6-9cba-382f3efaa657