# Physical Design Engineer, Forward Deployed Engineering

**Company:** [OpenAI](https://hotfix.jobs/companies/openai)
**Location:** San Francisco, CA
**Role:** Hardware Engineering
**Salary:** $260k – $302k/yr
**Experience:** 7+ years
**Skills:** Physical Design, Asic, Soc, Floorplanning, Place And Route, Clock-Tree Synthesis, Timing Closure, Power Analysis, Physical Verification, Static Timing Analysis, Eda Tools, Python, Tcl, Llm Systems
**Posted:** 2026-09-09

> Senior physical design specialist supporting semiconductor customer engagements, AI-assisted chip-design solutions, and broader forward-deployed engineering delivery. Requires deep ASIC/SoC backend implementation expertise, tapeout experience, EDA fluency, and at least 7 years with a bachelor’s degree or 5 years with a master’s.

## Job Description

## Responsibilities
- Serve as the physical design subject-matter expert for semiconductor customer engagements, advising on backend implementation workflows, constraints, and opportunities.
- Partner on customer discovery and scoping to define solution hypotheses, success criteria, and technical plans.
- Support customer-facing technical conversations as a trusted advisor.
- Shape AI-assisted solutions for floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff.
- Guide feasibility and integration decisions across chip design, verification, and physical design.
- Curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases.
- Build or guide prototypes, benchmarks, methodology experiments, and internal tools.
- Educate and mentor the broader team on physical design concepts, implementation flows, EDA tooling, and trade-offs.
- Surface customer feedback to Product and Research to inform roadmap, model behavior, and platform capabilities.
- Progressively take on customer discovery, solution architecture, prototype development, production deployment, and technical workstream ownership.

## Requirements
- BS with 7+ years, MS with 5+ years, or equivalent industry experience in physical design, physical implementation, or backend signoff for complex ASIC or SoC programs.
- Demonstrated success bringing complex designs through tapeout.
- Hands-on experience with floorplanning, place and route, clock-tree synthesis, timing closure, power analysis, physical verification, and signoff.
- Deep familiarity with EDA tools and flows for synthesis, place and route, static timing analysis, physical verification, equivalence checking, and power analysis.
- Strong understanding of physical design interactions with microarchitecture, RTL, verification, design methodology, libraries/PDKs, and system-level PPA trade-offs.
- Strong communication and collaboration skills for customer-facing and cross-functional technical work.
- Ability to operate as a consultative expert and advisor.
- Strong scripting and automation skills in Python, Tcl, or similar.
- Willingness to grow into broader Forward Deployed Engineering responsibilities, including hands-on solution building and customer-facing delivery.

## Nice-to-haves
- Experience across multiple semiconductor companies, design environments, or tool stacks.
- Experience with external customers, strategic accounts, or design partners in a technical advisory capacity.
- Experience defining or scaling evaluation workflows, benchmarks, or acceptance criteria.
- Exposure to adjacent design or verification workflows.
- Experience applying AI or LLM systems to semiconductor workflows.
- Experience in solutions engineering, field engineering, customer-facing technical delivery, or consultative technical roles.

## Compensation
- Annual salary: $260,000–$302,000

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