# Software Engineer, AI Accelerator Runtime

**Company:** [OpenAI](https://hotfix.jobs/companies/openai)
**Location:** San Francisco, CA
**Role:** Embedded Engineering
**Salary:** $266k – $445k/yr
**Skills:** C, C++, Rust, Concurrency, Synchronization, Dma, Caching, Memory Management, Operating Systems, Device Drivers, Firmware, Cycle-Accurate Simulation, Profiling, Virtual Memory
**Posted:** 2026-08-24

> Build the low-level runtime for a custom AI accelerator, including kernel scheduling, device memory management, synchronization, and hardware-software interfaces. The role requires strong systems programming experience and expertise in concurrency, memory semantics, simulation, and performance debugging.

## Job Description

## Responsibilities
- Design and implement the low-level device runtime for OpenAI custom silicon.
- Build kernel-launch scheduling, command submission, queueing, dependency tracking, and completion handling.
- Manage device memory spaces, allocation, virtual-to-physical mappings, data movement, and lifetimes across concurrent workloads.
- Implement synchronization primitives, events, barriers, streams, and ordering guarantees.
- Define interfaces between the runtime, drivers, firmware, compiler-generated code, kernels, and higher-level execution systems.
- Use event-based, cycle-accurate simulators to develop, validate, debug, and tune runtime behavior before and after silicon availability.
- Diagnose concurrency, memory-ordering, deadlock, race, correctness, and performance issues across software and hardware boundaries.
- Build tests, tracing, profiling, observability, and reproducible workloads for runtime correctness and performance.
- Partner with architecture and silicon teams on hardware-software interface improvements.

## Requirements
- Strong low-level systems programming experience in C, C++, Rust, or comparable environments.
- Experience building runtimes, drivers, firmware, operating-system components, accelerator software, or adjacent systems infrastructure.
- Understanding of concurrency, synchronization, asynchronous execution, queues, events, and memory-ordering semantics.
- Understanding of memory management, address spaces, DMA, caching, coherency, and hardware-software interfaces.
- Hands-on experience with event-based, cycle-accurate simulators or related architectural and performance models.
- Ability to reason quantitatively about scheduling, latency, throughput, utilization, contention, and resource tradeoffs.
- Skilled at debugging issues spanning software abstractions, device interfaces, and hardware behavior.
- Ability to work across compiler, kernel, architecture, verification, firmware, and silicon teams.

## Additional Information
- Candidates may need to meet legal status requirements under U.S. export control laws and regulations.

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