# Hardware Tools Engineer

**Company:** [OpenAI](https://hotfix.jobs/companies/openai)
**Location:** San Francisco, CA
**Role:** Embedded Engineering
**Salary:** $225k – $445k/yr
**Skills:** Rust, C++, Python, Verilog, Systemverilog, Llvm, Chisel, Firrtl, Mlir, Bazel
**Posted:** 2026-03-02

> Develops software tooling for hardware engineers, including compilers, IR transformations, simulation, and automation for AI-native silicon design. Requires strong CS fundamentals, proficiency in Rust/C++/Python, and familiarity with RTL and compilers.

## Job Description

## In this role you will:
- Build and improve the software tooling that makes hardware teams faster: compilation, IR transforms, RTL generation, simulation, debug, and automation.
- Extend and integrate hardware compiler stacks (frontends, IR passes, lowering, scheduling, codegen to Verilog/SystemVerilog) and connect them to real design workflows.
- Improve developer experience and reliability: reproducible builds, better error messages, faster iteration loops, and dependable CI and regression infrastructure.
- Work closely with designers and verification engineers to turn real pain points into durable tools.
- Dive into RTL when needed: read and reason about Verilog/SystemVerilog to debug issues, validate tool output, and improve debuggability.
- Be willing to go all the way down the stack when necessary, including gate-level views, synthesis results, and implementation artifacts.
- Help enable PPA optimization loops by building analysis and automation around area, timing, and power tradeoffs, and by improving tooling that impacts those outcomes.

## You might thrive in this role if:
- Demonstrated ability to build and maintain software (projects, internships, research, open source, or equivalent experience).
- Strong CS fundamentals: data structures, algorithms, debugging, and software design.
- Proficiency in at least one of **Rust**, **C++**, or **Python** (and willingness to learn the rest).
- Familiarity with digital design concepts and the ability to read RTL (**Verilog/SystemVerilog**) or equivalent hardware descriptions.
- Familiarity with compiler or IR-based ideas (representations, passes, transformations, lowering), through coursework or projects.
- Comfort operating in ambiguity and iterating quickly with users of your tools.

## Nice to have skills:
- Exposure to compiler and hardware toolchains such as **XLS/DSLX**, **LLVM**, **Chisel/FIRRTL**, **CIRCT/MLIR**, other novel hardware languages (e.g. HardCaml, SpinalHDL, Spade, PyMTL, Clash, BlueSpec, PyRope).
- Experience with Verilog tooling ecosystems (**Yosys/RTLIL**, **Verilator**, **Slang**) or writing tooling around them.
- Experience with build and test infrastructure (**Bazel**, CI systems, fuzzing, performance testing).
- Prior work touching synthesis, place and route, static timing analysis, or other PPA-related workflows.

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