# Physical Design Engineer

**Company:** [Cerebras Systems](https://hotfix.jobs/companies/cerebras-systems)
**Location:** Bengaluru, India
**Role:** Hardware Engineering
**Experience:** 7+ years
**Skills:** Physical Design, Synthesis, Place And Route, Static Timing Analysis, Timing Closure, Physical Verification, Drc, Lvs, Icv, Calibre, Ir/Em Analysis, Tcl, Python, Synopsys
**Posted:** 2026-05-06

> Performs physical design and verification for wafer-scale AI chip blocks, including synthesis, place and route, timing closure, physical sign-off, and full-chip integration. Requires 7+ years of experience, strong DRC/LVS and IR/EM expertise, and Tcl/Python scripting skills.

## Job Description

## Responsibilities
- Perform physical design tasks including synthesis, place and route, timing, and block closure/sign-off.
- Work across physical design and implementation activities for wafer-scale design integration.
- Collaborate closely with RTL teams and support full-chip integration of physical design blocks.
- Optimize designs for power, performance, and area.
- Perform block and full-chip physical verification, including DRC and LVS resolution.
- Conduct IR/EM analysis and resolve related issues.
- Contribute to full-chip floor planning and integration.
- Develop scripting and flow enhancements using Tcl and Python.
- Help optimize RTL for physical design.
- Take on leadership responsibilities after ramping up on wafer-scale design.

## Requirements
- 7+ years of physical design or verification experience.
- Strong experience with block/subsystem timing closure.
- Strong knowledge of block-level and full-chip physical verification methodologies.
- Expertise in power, performance, and area optimization.
- Experience with block physical design, physical design verification (PDV), and IR analysis.
- Expertise with ICV or Calibre for resolving block and full-chip DRC and LVS issues.
- Expertise in IR/EM analysis and resolution.
- Good understanding of full-chip floor planning and integration.
- Strong scripting ability with Tcl and Python.
- Ability to learn, grow, and contribute effectively within a team.
- BSEE, MSEE, or Ph.D. in Electrical Engineering preferred.

## Nice to Have
- Experience with the complete physical design flow.
- Knowledge of the Synopsys tool suite.
- Experience with synthesis and static timing analysis (STA).

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