# Research Engineer - Mid-Training

**Company:** [Voltai](https://hotfix.jobs/companies/voltai)
**Location:** Palo Alto, CA
**Role:** ML Engineering
**Skills:** LLMs, Foundation Models, Rtl, Netlists, Pdks, Simulation Logs, Scaling Laws, Synthetic Data, Testbenches, Verification Traces, Evals, Timing Closure, PyTorch, Gpu Training, Reinforcement Learning
**Posted:** 2025-11-06

> Trains frontier LLMs on semiconductor design/verification data (RTL, netlists, PDKs) for automated chip development. Develops synthetic data generation, model distillation, evals, and scales training across thousands of GPUs.

## Job Description

## Responsibilities
- Train frontier models to become highly knowledgeable semiconductor design and verification experts for reinforcement learning and automated chip development.
- Develop methods for generating and curating synthetic design data, performing model distillation, and enabling continual learning at scale.
- Work with hardware engineers, RL researchers, and verification specialists to create evals that guide design data quality and model improvement.
- Collaborate with compute engineers to scale efficient training across thousands of GPUs and RL environments.
- Build high-performance tools to investigate how data and simulation shape model-driven design intelligence.

## Requirements
- Experience training LLMs or foundation models on semiconductor design and verification corpora (e.g., RTL, netlists, PDKs, simulation logs).
- Modeling design scaling laws and optimizing compute budgets for chip-design-specific workloads.
- Generating large-scale synthetic design data (e.g., RTL variants, testbenches, verification traces).
- Building evals that correlate with downstream design metrics (e.g., timing closure, power, area, verification coverage).

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**Apply:** https://hotfix.jobs/jobs/541e22c3-3e25-46db-85ec-2ac1edf14d90
**Canonical:** https://hotfix.jobs/jobs/541e22c3-3e25-46db-85ec-2ac1edf14d90