# Staff SoC RTL Engineer

**Company:** [Quadric](https://hotfix.jobs/companies/quadric)
**Location:** Burlingame, CA
**Role:** Hardware Engineering
**Salary:** $175k – $230k/yr
**Experience:** 7+ years
**Skills:** systemverilog, verilog, soc design, asic design, computer architecture, low-power design, third-party ip integration, noc, pcie, ddr, vcs, fpga design, logic synthesis, performance modeling, hardware security
**Posted:** 2026-08-06

> Design and integrate SoC RTL subsystems, third-party IP, and architecture for next-generation edge AI processors. The role requires 5+ years of SoC/ASIC front-end experience, strong SystemVerilog or Verilog skills, and expertise in computer architecture, low-power design, and subsystem development.

## Job Description

## Responsibilities

### SoC Subsystem Development & IP Integration
- Own SoC-level subsystem development and seamless integration with third-party IP, including NoC, PCIe/UCIe interfaces, DDR, and security IP.
- Contribute to SoC architecture definition by understanding application requirements.
- Package designs for customer releases and iterate based on customer feedback.

### PPA Optimization & Timing Closure
- Own Power, Performance, and Area (PPA) optimization strategies at the SoC level.
- Apply low-power digital design techniques to optimize hardware efficiency.
- Contribute to timing closure across front-end, back-end, and final tapeout stages.
- Balance single-stream latency against scaled throughput performance.

## Requirements
- Bachelor's, master's, or Ph.D. degree in Electrical Engineering, Computer Engineering, or a related field.
- Minimum **5+ years** of hands-on SoC/ASIC front-end design and integration experience.
- Proficiency in SystemVerilog or Verilog.
- Strong background in computer architecture and low-power digital design techniques.
- Deep technical knowledge in at least one subsystem: memory, I/O, or compute.
- Proven experience with SoC subsystems and third-party IP.
- Working knowledge of VCS and Verilog/C co-simulation.

## Nice-to-Haves
- Experience in logic synthesis and performance modeling.
- Experience in FPGA design.
- Familiarity with automotive safety standards, including ASIL.
- Familiarity with hardware security standards.

## Compensation & Benefits
- Base salary range: **$175,000–$230,000**.
- Eligibility for equity and a discretionary annual performance bonus, as applicable to the role and level.
- Medical, dental, and vision insurance from day one, with premiums covered at 99% for employees.
- Company-paid life insurance and voluntary supplemental life insurance.
- Short-term and long-term disability insurance.
- Commuter support, including parking or Caltrain reimbursement.
- FSA and HSA.
- Paid parental leave.
- 401(k) retirement plan.
- Flexible paid time off.
- Winter holiday shutdown.
- Catered lunch each day in the office.

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