# Design Validation Test - Lead/Principal Engineer

**Company:** [Cerebras Systems](https://hotfix.jobs/companies/cerebras-systems)
**Location:** Sunnyvale, CA
**Role:** DevOps / SRE
**Salary:** $175k – $275k/yr
**Experience:** 8+ years
**Skills:** Pcie, Ethernet, I2C, Spi, Usb, Oscilloscopes, Logic Analyzers, Power Analyzers, Python, Power Integrity, Ir Drop, Ripple Analysis, Bert, Vna
**Posted:** 2026-04-15

> Leads end-to-end Design Validation Test (DVT) for complex electrical boards and systems, including power delivery, high-speed I/O validation, debug, and root-cause analysis. Requires 8+ years experience in hardware validation, strong EE skills, and lab equipment proficiency.

## Job Description

## What You’ll Own

### 1) Board / Subassembly DVT (EE-heavy)
- Own DVT for complex PCBAs and subassemblies from first power‑on through design sign‑off.
- **Power validation**: power‑up/down sequencing, regulator/hotswap behavior, rail margining, DC IR drop, and AC noise/ripple characterization.
- Clock distribution validation and high‑speed I/O interface validation (e.g., Ethernet/PCIe-class links, board‑to‑board connectors and cabling).
- Low‑speed system management interface validation (e.g., I2C/SPI/USB) and debug of intermittent or systemic failures.
- Stress/environmental testing (extended runtime, temperature cycling) and characterization under margined conditions.

### 2) System-level DVT (integration + electro-mechanical)
- Own system integration validation planning and execution across representative configurations and operating envelopes.
- Drive readiness and execution across lab and chamber environments, including dependency management (test scripts, instrumentation, SW readiness, sample availability).
- Validate and debug system-level issues spanning electrical, mechanical, thermal, and optics interactions.
- Partner with reliability and manufacturing teams to ensure DVT coverage supports ramp readiness and reduces escapes.

## Key Responsibilities

### DVT Strategy, Plans, and Coverage
- Define a risk‑based DVT strategy spanning board/subassembly engineering validation through system integration validation.
- Author and maintain DVT plans, procedures, and reports with crisp pass/fail criteria and coverage rationale.
- Establish stage gates and readiness reviews for execution quality (fixtures, instrumentation, scripts, SW readiness).

### Hands-on Validation, Debug, and Closure
- Build and own benchtop and rack-level validation setups that are repeatable and automation‑friendly.
- Lead RCA for validation failures; drive corrective actions with design teams; verify fixes through re‑test and data review.
- Execute and interpret power integrity/stability measurements (voltage/current stability, droop, ripple/noise, IR drop) and close gaps to requirements.
- Validate high‑speed interconnect performance and margin; isolate failures across channel, connector/cable, PHY, and firmware/diagnostics layers.

### DVT Infrastructure, Automation, and Data
- Partner with diagnostics/software to improve DVT throughput via scripting, logging, and standardized test stages.
- Define required data capture and reporting standards to accelerate debug and support release gating.
- Drive continual improvements to test coverage, efficiency, and repeatability across builds.

### Cross-functional Technical Leadership
- Align EE/ME/FW/Diagnostics/Reliability/Manufacturing on priorities, schedules, and closure criteria.
- Influence design-for-testability improvements (debug visibility, margining hooks, instrumentation points, serviceability).

## Minimum Qualifications
- BS/MS in Electrical or Computer Engineering (or equivalent experience).
- 8–15+ years of hardware validation/DVT experience on complex board and system-level products.
- Demonstrated ownership of board bring‑up and DVT execution: test plan creation, instrumentation, debug, and closure.
- Strong background in **power delivery validation** and measurement (sequencing, margining, droop, ripple/noise, IR drop).
- Strong background in **high‑speed I/O validation** and debug (PCIe/Ethernet‑class links; channel and system-level troubleshooting).
- Proficiency with lab equipment: **oscilloscopes**, **logic analyzers**, **power supplies/analyzers**, **DC electronic loads**; VNAs/BERTs as applicable.
- Strong written and verbal communication; ability to present results and drive decisions with data.

## Preferred / Nice-to-Have
- Experience with rack-scale and/or liquid-cooled systems; validation in environmental chambers.
- Experience supporting compliance/safety/EMC efforts as part of DVT readiness.
- **Python** (or similar) for test automation and data analysis; experience integrating results into dashboards/CI workflows.
- Experience mentoring engineers/technicians as an informal technical leader.

## Compensation
Base salary range: **$175,000 to $275,000** annually. Actual compensation may include bonus and equity.

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