# Design Verification Engineer

**Company:** [OpenAI](https://hotfix.jobs/companies/openai)
**Location:** San Francisco, CA
**Role:** QA Engineering
**Salary:** $226k – $445k/yr
**Experience:** 3+ years
**Skills:** Systemverilog, Uvm, Vcs, Questa, Verdi, Computer Architecture, Rtl, Soc Verification, Memory Systems, Interconnects
**Posted:** 2025-10-29

> Design Verification Engineer verifies custom silicon for AI/ML accelerators, owning testbenches for IP blocks, subsystems, and SoC using SystemVerilog/UVM. Requires 3+ years experience, proficiency in verification tools, and knowledge of computer architecture.

## Job Description

## Responsibilities
- Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
- Define verification plans based on architecture and microarchitecture specs.
- Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
- Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
- Drive bug triage, root cause analysis, and work closely with design teams on resolution.
- Contribute to regression infrastructure, coverage analysis, and closure for both block- and top-level environments.

## Requirements
- BS/MS in EE/CE/CS or equivalent with **3+ years** of experience in hardware verification.
- Proven success verifying complex IP or SoC designs in industry-standard flows.
- Proficient in **SystemVerilog**, **UVM**, and common simulation and debug tools (e.g., **VCS**, **Questa**, **Verdi**).
- Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.

## Nice-to-Haves
- Familiarity with performance modeling, formal verification, or emulation.

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